R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 472
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 442 of 583
27. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins and P1_0 to P1_3.
27.1
Table 27.1
Notes:
A/D conversion method
Analog input voltage
Operating clock φAD
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
(φAD = fAD)
Table 27.1 lists the A/D Converter Performance. Figure 27.1 shows a Block Diagram of A/D Converter.
1. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
2. When 4.0 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 20 MHz or below.
3. The conversion rate per pin is minimum 43 φAD cycles for 8-bit and 10-bit resolution.
in 10-bit mode and FFh in 8-bit mode.
When 3.2 V ≤ AVCC < 4.0 V, the frequency of φAD must be 16 MHz or below.
When 3.0 V ≤ AVCC < 3.2 V, the frequency of φAD must be 10 MHz or below.
When 2.2 V ≤ AVCC < 3.0 V, the frequency of φAD must be 5 MHz or below.
The φAD frequency should be 2 MHz or above.
Overview
(3)
Item
A/D Converter Performance
Preliminary specification
Specifications in this manual are tentative and subject to change.
(1)
(2)
Nov 05, 2008
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
fAD, fAD divided by 2, fAD divided by 4, fAD divided by 8
(fAD=f1 or fOCO-F)
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φAD = 20 MHz
AVCC = Vref = 3.3 V, φAD = 16 MHz
AVCC = Vref = 3.0 V, φAD = 10 MHz
AVCC = Vref = 2.2 V, φAD = 5 MHz
One-shot mode, repeat mode 0, repeat mode 1, single sweep mode,
and repeat sweep mode
4 pins (AN8 to AN11)
• Software trigger
• Timer RC
• External trigger
Minimum 43 φAD cycles
(Refer to 27.3.3 A/D Conversion Start Condition.)
• 8-bit resolution
• 10-bit resolution ±3 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
Performance
27. A/D Converter
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