C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 182

• Manufacturer Part Number: C8051F930-GQ
• Description: IC 8051 MCU 64K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F930-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 23x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F930DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 23-ch x 10-bit
• No. Of I/o's: 24
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1466

C8051F93x-C8051F92x
18.2. Power-Fail (VDD/DC+ Supply Monitor) Reset
C8051F93x-C8051F92x devices have a VDD/DC+ Supply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes VDD/DC+ to drop below V
be driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD/DC+ returns to a
level above V
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD/DC+ supply
monitor is enabled and selected as a reset source. The enable state of the VDD/DC+ supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD/DC+ supply monitor is de-selected as a reset source and disabled by software, then a software reset
is performed, the VDD/DC+ supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V
above V
source select state of the VDD/DC+ supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD/DC+ supply falls below the V
interrupt. See Section “12. Interrupt Handler” on page 133 for more details.
Important Note: To protect the integrity of Flash contents, the VDD/DC+ supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD/DC+ supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
182
V
V
POR
V
WARN
POR
RST
VDDOK
SLEEP
while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
RST
RST
, the CIP-51 will be released from the reset state.
Power-Fail Reset
Active Mode
Figure 18.3. Power-Fail Reset Timing Diagram
POR
VDD/DC+
WARN
VBAT
. A large capacitor can be used to hold the power supply voltage
threshold. The VDDOK bit can be configured to generate an
Rev. 1.1
RAM Retained - No Reset
Sleep Mode
RST
Note: W akeup signal
will cause the RST pin to
required after new
battery insertion
t