C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 206

IC 8051 MCU 64K FLASH 32-LQFP

C8051F930-GQ

Manufacturer Part Number
C8051F930-GQ
Description
IC 8051 MCU 64K FLASH 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Datasheets

Specifications of C8051F930-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 23x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F930DK
Minimum Operating Temperature
- 40 C
On-chip Adc
23-ch x 10-bit
No. Of I/o's
24
Ram Memory Size
4KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1466

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F930-GQ
Manufacturer:
SILICON
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C8051F930-GQ
Manufacturer:
Silicon Laboratories Inc
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C8051F930-GQR
Manufacturer:
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Manufacturer:
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C8051F93x-C8051F92x
20.2.5. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section “12. Interrupt Handler” on page 133, Section “14. Power
Management” on page 156, and Section “18. Reset Sources” on page 180 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
20.2.6. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during
crystal startup to determine when oscillation has started and is nearly stable. The output of this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
20.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset the device at a specific time. See Section “12. Interrupt
Handler” on page 133, Section “14. Power Management” on page 156, and Section “18. Reset Sources”
on page 180 for more information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after an alarm occurs. When using Auto Reset, the Alarm match value should always
be set to 1 count less than the desired match value. Auto Reset can be enabled by writing a 1 to ALRM
(RTC0CN.2).
20.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
The following steps can be used to read the current timer value:
20.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers.
If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm
event.
206
The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal oscil-
lator, the output of CLKVLD is not valid.
This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure.
The missing SmaRTClock detector (CLKFAIL) should be used for this purpose.
RTC0XCN.
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRT-
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
Clock timer.
Rev. 1.1

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