C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 312

• Manufacturer Part Number: C8051F930-GQ
• Description: IC 8051 MCU 64K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F930-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 23x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F930DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 23-ch x 10-bit
• No. Of I/o's: 24
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1466

C8051F93x-C8051F92x
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 26.5, where PCA0L is the value of the PCA0L register
at the time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
26.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
•
•
The PCA clock source and idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 26.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 26.3 lists some example
timeout intervals for typical system clocks.
312
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2 – CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH5.
Notes:
System Clock (Hz)
Equation 26.5. Watchdog Timer Offset in PCA Clocks
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Offset
24,500,000
24,500,000
24,500,000
3,062,500
3,062,500
3,062,500
Table 26.3. Watchdog Timer Timeout Intervals
of 0x00 at the update time.
32,000
32,000
32,000
=
2
2
2

256 PCA0CPL5

PCA0CPL5
Rev. 1.1
255
128
255
128
255
128
32
32
32

+

256 PCA0L
Timeout Interval (ms)
–
24576
12384
129.5
3168
32.1
16.2
33.1
257
4.1

1