C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 323

IC 8051 MCU 64K FLASH 32-LQFP

C8051F930-GQ

Manufacturer Part Number
C8051F930-GQ
Description
IC 8051 MCU 64K FLASH 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Datasheets

Specifications of C8051F930-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 23x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F930DK
Minimum Operating Temperature
- 40 C
On-chip Adc
23-ch x 10-bit
No. Of I/o's
24
Ram Memory Size
4KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1466

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F930-GQ
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
C8051F930-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F930-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F930-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
D
Revision 1.0 to Revision 1.1
OCUMENT
On front page, clarified that the SmaRTClock oscillator has an internal self-oscillate mode.
Updated block diagrams in system overview.
Updated mechanical package drawings for all three packages.
Added a new Absolute Maximum Rating specification for maximum total current through all Port pins.
Added additional data points for Sleep Mode current.
ADC0 Maximum SAR Clock frequency and Minimum Settling Time specifications updated. Also update
the turn-on time specification for the internal high speed VREF.
Updated Port I/O, Reset, IREF0, Comparator, and dc-dc converter specification tables.
Expanded note in ADC Data Register indicating that ADC0H:ADC0L should not be written when the
SYNC bit is set to 1.
Updated Figure 5.8 to correct order of operations in the temperature sensor transfer function equation.
Updated text which referred to the address as A[15:0]. The 12-bit address should be A[11:0].
Added a note to the FLSCL register description describing the need for a dummy 3-byte MOV
instruction following any operation that clears the BYPASS bit. Also updated the FLWR register
description indicating that writes to FLWR have no effect on system operation.
In the Flash chapter, added a note which says that
to Flash memory at addresses higher than 0x00FF.
Updated chapter text and figures in the power management chapter.
Added a note to the CRC0CN register description describing the need for a dummy 3-byte MOV
instruction following any operation that initiates an automatic CRC operation.
Updated dc-dc converter diagram to properly show parasitic inductance.
Removed the requirement that the output voltage has to be at least 0.2V higher than the input voltage.
Added several clarifications to the dc-dc converter chapter text.
Updated the CLKSEL register description.
In Table 19.1, changed the high end of the crystal frequency range to 25 MHz.
Globally changed “smaRTClock” to “SmaRTClock”.
Updated the RTC0PIN register description.
Updated recommend instruction timing for accessing indirect SmaRTClock registers. Polling ‘BUSY’ to
wait for data transfer is no longer required as long as the recommended instruction timing is followed.
Updated recommended crystal characteristics / operating conditions.
Added information on how to perform SmaRTClock oscillation robustness test.
Updated Port I/O Cell Diagram.
Corrected description of XBR0, bit 0. Also made minor updates to Port I/O chapter text.
Emphasized that port match is not available on P1.6 and P1.7 for ‘F931/’F921 devices.
Added a note to refer to the C8051F930 Errata when using the SMBus Hardware Acknowledge
Feature.
Updated text which refers to Timer 3, but references bits in the Timer 2 control register.
Updated text in PCA0 chapter related to the watchdog timer. The watchdog timer uses PCA module 5.
Re-formatted the PCA0CPMn register description to fit on a single page.
C
HANGE
L
IST
Rev. 1.1
8-bit MOVX instructions cannot be used to erase or write
C8051F93x-C8051F92x
323

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