M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 16

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an
arithmetic operation and 3 flags which decide MCU operation.
Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
• Bit 0: Carry flag (C)
• Bit 1: Zero flag (Z)
• Bit 2: Interrupt disable flag (I)
• Bit 3: Decimal mode flag (D)
Table 8
Set instruction
Clear instruction
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate
instruction.
The Z flag is set to “1” if the result of an immediate arithmetic
operation or a data transfer is “0”, and set to “0” if the result is
anything other than “0”.
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can be used for decimal arithmetic.
Set and clear instructions of each bit of processor status register
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C flag
SEC
CLC
Z flag
−
−
I flag
SEI
CLI
D flag
SED
CLD
• Bit 4: Break flag (B)
• Bit 5: Index X mode flag (T)
• Bit 6: Overflow flag (V)
• Bit 7: Negative flag (N)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. When the BRK instruction
is generated, the B flag is set to “1” automatically. When the
other interrupts are generated, the B flag is set to “0”, and the
processor status register is pushed onto the stack.
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to -128.
When the BIT instruction is executed, bit 6 of the memory
location operated on by the BIT instruction is stored in the
overflow flag.
The N flag is set to “1” if the result of an arithmetic operation
or data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the BIT
instruction is stored in the negative flag.
B flag
−
−
T flag
SET
CLT
V flag
CLV
−
N flag
−
−