M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 46

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
SERIAL INTERFACE
• SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
Fig. 33 Block diagram of clock synchronous serial I/O1
Fig. 34 Operation of clock synchronous serial I/O1 function
Write pulse to receive/transmit
buffer register
φSOURCE
Receive enable signal S
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
P4
P4
P4
P4
Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or
3
2
/S
/S
0
1
/R
/T
Note1: φSOURCE indicates the followings:
RDY1
CLK1
X
X
D
D
May 20, 2008 Page 44 of 134
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
(1)
Serial output TxD
after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
is output continuously from the TxD pin.
Serial input RxD
•X
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
IN
input in the frequency/2, 4, or 8 mode
BRG count source selection bit
F/F
RDY
TBE = 0
1/4
Falling-edge detector
TBE = 1
TSC = 0
Receive buffer register
Receive shift register
D
D
0
0
Data bus
Transmit buffer register
Transmit shift register
Data bus
Frequency division ratio 1/(n+1)
Address 0018
Shift clock
D
D
1
1
Baud rate generator
Serial I/O1 synchronous
Shift clock
Address 001C
Address 0018
clock selection bit
D
D
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O mode selection bit of the serial I/O1 control register
to “1”.
For clock synchronous serial I/O1, the transmitter and the
receiver must use the same clock. If an internal clock is used,
transfer is started by a write signal to the TB/RB.
16
2
2
Clock control circuit
Clock control circuit
16
16
D
D
Serial I/O1 control register
3
3
Receive buffer full flag (RBF)
Transmit interrupt source selection bit
Serial I/O1 status register
1/4
D
D
4
4
Receive interrupt request (RI)
Transmit buffer empty flag (TBE)
Transmit shift completion flag (TSC)
D
D
5
5
Transmit interrupt request (TI)
Address 001A
D
D
Address 0019
6
6
Overrun error (OE)
detection
RBF = 1
TSC = 1
D
D
7
7
16
16