C8051F046-GQR Silicon Laboratories Inc, C8051F046-GQR Datasheet - Page 32
C8051F046-GQR
Manufacturer Part Number
C8051F046-GQR
Description
IC 8051 MCU 32K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F046-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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C8051F040/1/2/3/4/5/6/7
1.8.
The C8051F040/1 devices have an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer
and programmable gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit per-
formance with an INL of ±1LSB. C8051F042/3/4/5/6/7 devices include a 10-bit SAR ADC with similar spec-
ifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output
and an external VREF pin. On C8051F040/2/4/6 devices, ADC0 has its own dedicated VREF0 input pin;
on C8051F041/3/5/7 devices, the ADC0 uses the VREFA input pin and, on the C8051F041/3, shares it
with the 8-bit ADC2. The on-chip 15 ppm/°C voltage reference may generate the voltage reference for the
on-chip ADCs or other system components via the VREF output pin.
The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers.
One input channel is tied to an internal temperature sensor, while the other eight channels are available
externally. Each pair of the eight external input channels can be configured as either two single-ended
inputs or a single differential input. The system controller can also put the ADC into shutdown mode to
save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set to 0.5, 1, 2, 4, 8, or 16
and is software programmable. The gain stage can be especially useful when different ADC input channels
have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc
offset (in differential mode, a DAC could be used to provide the dc offset).
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software
events, external HW signals, or a periodic timer overflow signal. Conversion completions are indicated by a
status bit and an interrupt (if enabled). The resulting 10- or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data
is within or outside of a specified range. The ADC can monitor a key voltage continuously in background
mode, but not interrupt the controller unless the converted data is within the specified window.
32
HVAIN +
HVAIN -
AIN0.0
AIN0.1
AIN0.2
AIN0.3
12/10-Bit Analog to Digital Converter
Port 3
Pins
Analog Multiplexer
AGND
HVDA
SENSOR
TEMP
Figure 1.12. 10/12-Bit ADC Block Diagram
+
+
+
-
-
-
AMUX
(SE or
9-to-1
DIFF)
Programmable Gain
(C8051F040/1/2/3 Only)
X
Amplifier
Configuration, Control, and Data
External VREF
+
-
DAC0 Output
Rev. 1.5
AV+
Registers
Pin
12/10-Bit
ADC
VREF
SAR
Start
Conversion
Window Compare
12
Logic
Write to AD0BUSY
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
ADC Data
Registers
Conversion
Complete
Compare
Window
Interrupt
Interrupt
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