DF2210CUNP24V Renesas Electronics America, DF2210CUNP24V Datasheet - Page 166
DF2210CUNP24V
Manufacturer Part Number
DF2210CUNP24V
Description
MCU 16BIT FLASH 3V 32K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2210CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2210CUNP24V
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Selection of Interrupt Source: An activation factor is directly input to each channel of the
DMAC. The activation factors for each channel of the DMAC are selected by the DTF3 to DTF0
bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation
factors are managed by the DMAC. By setting the DTA bit to 1, the interrupt factor which was the
activation factor for that DMAC cannot act as the CPU interrupt factor.
Interrupt factors other than the interrupts managed by the DMAC is CPU interrupt request.
Determination of Priority: The activation source is directly input to each channel of DMAC.
Operation Order: If the same interrupt is selected as the DMAC activation factor or CPU
interrupt factor, these operate independently. They operate in accordance with the respective
operating states and bus priorities.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC's DMABCR.
Rev.7.00 Dec. 24, 2008 Page 110 of 698
REJ09B0074-0700
peripheral
On-chip
module
IRQ
interrupt
Interrupt source
clear signal
Interrupt
request
Figure 5.7 Interrupt Control for DMAC
Interrupt controller
Selection
circuit
Disenable
signal
DMAC
Determination of
Control logic
priority
Clear
signal
CPU interrupt
request vector
number
I, I2 to I0
CPU
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