R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 378
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 341 of 802
20.4.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) for Output Compare
Notes:
1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the
2. This setting is enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.
3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to
4. This setting is enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0140h (TRDCR0), 0150h (TRDCR1)
TRDFCR register is 1 (external clock input enabled).
0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
synchronously).
Symbol
Symbol
CKEG0 External clock edge select bit
CKEG1
CCLR0 TRDi counter clear select bit
CCLR1
CCLR2
Bit
TCK0
TCK1
TCK2
Function
CCLR2
b7
0
Count source select bit
CCLR1
b6
0
Oct 30, 2009
Bit Name
CCLR0
b5
0
CKEG1
(3)
b4
0
b2 b1 b0
b4 b3
b7 b6 b5
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRDCLK input
1 1 0: Do not set.
1 1 1: Do not set.
0 0: Count at the rising edge
0 1: Count at the falling edge
1 0: Count at both edges
1 1: Do not set.
0 0 0: Clear disabled (free-running operation)
0 0 1: Clear by compare match with the TRDGRAi
0 1 0: Clear by compare match with the TRDGRBi
0 1 1: Synchronous clear (clear simultaneously with
1 0 0: Do not set.
1 0 1: Clear by compare match with the TRDGRCi
1 1 0: Clear by compare match with the TRDGRDi
1 1 1: Do not set.
CKEG0
b3
0
register
register
other timer RDi counter)
register
register
TCK2
b2
0
(1)
Function
or fC2
TCK1
b1
0
(2)
(4)
TCK0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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