R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 484
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Quantity
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- Download datasheet (16Mb)
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 447 of 802
22.2.2
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0171h
The TRGCNTC register is used in phase counting mode. This register sets its count conditions.
Symbol CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0
CNTEN0 Counter enable bit 0
CNTEN1 Counter enable bit 1
CNTEN2 Counter enable bit 2
CNTEN3 Counter enable bit 3
CNTEN4 Counter enable bit 4
CNTEN5 Counter enable bit 5
CNTEN6 Counter enable bit 6
CNTEN7 Counter enable bit 7
Bit
Symbol
Timer RG Count Control Register (TRGCNTC)
b7
0
b6
0
Oct 30, 2009
Bit Name
b5
0
b4
0
0: Disabled
1: Decrement
0: Disabled
1: Decrement
0: Disabled
1: Decrement
0: Disabled
1: Decrement
0: Disabled
1: Increment
0: Disabled
1: Increment
0: Disabled
1: Increment
0: Disabled
1: Increment
When TRGCLKA input is high and
at the rising edge of TRGCLKB input
When TRGCLKB input is low and
at the rising edge of TRGCLKA input
When TRGCLKA input is low and
at the falling edge of TRGCLKB input
When TRGCLKB input is high and
at the falling edge of TRGCLKA input
When TRGCLKB input is low and
at the falling edge of TRGCLKA input
When TRGCLKA input is high and
at the falling edge of TRGCLKB input
When TRGCLKB input is high and
at the rising edge of TRGCLKA input
When TRGCLKA input is low and
at the rising edge of TRGCLKB input
b3
0
b2
0
Function
b1
0
b0
0
22. Timer RG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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