DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 335
DF38602RFT10
Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet
1.DF38602RFT10.pdf
(554 pages)
Specifications of DF38602RFT10
Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10
HD64F38602RFT10
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
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[1]
[2]
[3]
[4]
[5]
[6]
[7]
No
No
Dummy read on SSRDR
Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)
RE = 0, RSSTP = 0
Read receive data
Read receive data
Set RSSTP to 1
Last reception?
Read ORER
Read ORER
Read RDRF
Read RDRF
Initialization
ORER = 1?
ORER = 1?
RDRF = 1?
RDRF = 1?
in SSRDR
in SSRDR
Start
End
No
No
Yes
No
Yes
Yes
Yes
Yes
Overrun error
Section 15 Synchronous Serial Communication Unit (SSU)
processing
[1] After setting each register in the SSU,
[2] Determine whether the last one byte of
[3][6] When a receive error occurs, clear the
[4] Confirm that the RDRF bit is 1. If the RDRF
[5] Before the last one byte of data is received,
[7] Confirm that the RDRF bit is 1. To end
dummy read on SSRDR is performed
and reception is started.
data is received. When the last one byte
of data is received, set to stop reception
after the data is received.
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
set the RSSTP bit to 1 and reception is stopped
after the data is received.
reception, clear the RE and RSSTP bits to
0 and then read the last receive data. If the
SSRDR bit is read before clearing the RE bit,
reception is started again.
ORER flag to 0 after the ORER flag in
SSSR is read and an appropriate error
processing is performed. When the ORER
flag is set to 1, transmission/reception
cannot be started again.
Rev. 3.00 May 15, 2007 Page 301 of 518
REJ09B0152-0300
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