MC908LK24CPBE Freescale Semiconductor, MC908LK24CPBE Datasheet - Page 145
MC908LK24CPBE
Manufacturer Part Number
MC908LK24CPBE
Description
IC MCU 8BIT 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC908LK24CPBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
HC08LK
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC908LK24CPBE
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Part Number:
MC908LK24CPBE
Manufacturer:
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9.4.1 External Pin Reset
9.4.2 Active Resets from Internal Sources
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
The RST pin circuit includes an internal pull-up device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 ICLK cycles, assuming that neither the POR nor the LVI
was the source of the reset. See
Figure 9-4
All internal reset sources actively pull the RST pin low for 32 ICLK cycles
to allow resetting of external peripherals. The internal reset signal IRST
continues to be asserted for an additional 32 cycles (see
internal reset can be caused by an illegal address, illegal opcode, COP
timeout, LVI, or POR (see
For LVI or POR resets, the SIM cycles through 4096 + 32 ICLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in
Figure
CGMOUT
RST
IAB
Reset Type
All others
POR/LVI
9-5.
PC
System Integration Module (SIM)
shows the relative timing.
Figure 9-4. External Reset Timing
Table 9-2. PIN Bit Set Timing
Figure
Number of Cycles Required to Set PIN
Table 9-2
9-6).
4163 (4096 + 64 + 3)
67 (64 + 3)
for details.
System Integration Module (SIM)
Reset and System Initialization
VECT H VECT L
Figure
Data Sheet
9-5). An
145
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