MCHC908LK24CFQE Freescale Semiconductor, MCHC908LK24CFQE Datasheet - Page 148
MCHC908LK24CFQE
Manufacturer Part Number
MCHC908LK24CFQE
Description
IC MCU 24K FLASH 8MHZ SPI 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MCHC908LK24CFQE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Controller Family/series
HC08
No. Of I/o's
48
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LK
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Price
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System Integration Module (SIM)
9.4.2.3 Illegal Opcode Reset
9.4.2.4 Illegal Address Reset
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
9.4.2.6 Monitor Mode Entry Module Reset (MODRST)
Data Sheet
148
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 + 32 ICLK
cycles. Thirty-two ICLK cycles later, the CPU is released from reset to
allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.
The monitor mode entry module reset (MODRST) asserts its output to
the SIM when monitor mode is entered in the condition where the reset
vectors are blank ($FF). (See
MODRST gets asserted, an internal reset occurs. The SIM actively pulls
down the RST pin for all internal reset sources.
DD
voltage falls to the LVI trip falling voltage, V
System Integration Module (SIM)
Section 10. Monitor ROM
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
TRIPF
(MON).) When
. The LVI bit in
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