HD64F3644H Renesas Electronics America, HD64F3644H Datasheet - Page 350
HD64F3644H
Manufacturer Part Number
HD64F3644H
Description
IC H8 MCU FLASH 32K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644H
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 10 Serial Communication Interface
Simultaneous Transmit/Receive: Figure 10.20 shows an example of a flowchart for a
simultaneous transmit/receive operation. This procedure should be followed for simultaneous
transmission/reception after initializing SCI3.
Rev. 6.00 Sep 12, 2006 page 328 of 526
REJ09B0326-0600
Figure 10.20 Example of Simultaneous Data Transmission/Reception Flowchart
3
1
2
transmission/reception?
Read receive data
Clear bits TE and
Read bit TDRE
Read bit RDRF
RE to 0 in SCR
Write transmit
Continue data
Read bit OER
data to TDR
RDRF = 1?
TDRE = 1?
OER = 1?
in SSR
in RDR
in SSR
in SSR
Start
End
Yes
No
Yes
No
4
Yes
No
No
Yes
Overrun error
processing
(Synchronous Mode)
1.
2.
3.
4.
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before transmitting the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission
and reception cannot be resumed if bit OER is
set to 1. See figure 10.18 for details on overrun
error processing.
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