DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 239
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 239 of 794
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Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be
Table 9.30 Output Level Select Function
Note: The reverse phase waveform initial output value changes to active level after elapse of the
Bit
3
2
1
0
Bit 1
OLSN
0
1
dead time after count start.
2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
3. Clearing the TOCS bit to 0 makes this bit setting valid.
Bit Name
TOCL
TOCS
OLSN
OLSP
Initial Output
High level
Low level
written to the bit.
control.
Initial
Value
0
0
0
0
Active Level
Low level
High level
R/W
R/(W)*
R/W
R/W
R/W
1
Description
TOC Register Write Protection*
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
1: Write access to the TOCS, OLSN, and OLSP bits is
TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.30.
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.31.
Output Level Select N*
Output Level Select P*
Up Count
High level
Low level
enabled
disabled
Function
Compare Match Output
Rev. 5.00 Mar. 06, 2009 Page 219 of 770
3
3
Down Count
Low level
High level
2
REJ09B0243-0500
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