M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 308
M30840SGP#U5
Manufacturer Part Number
M30840SGP#U5
Description
IC M32C/84 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30843FWGPU5.pdf
(531 pages)
Specifications of M30840SGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30840SGP#U5M30840SGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
3
. v
J
2
0
C
Figure 22.11 Counter Increment/Decrement Mode
1
9
0 .
8 /
B
0
(1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows)
(2) When the IT bit is set to "1" (bit 14 in the base timer overflows)
(3) When the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching with the G1PO0 register)
1
4
0
3
G
J
6
u
o r
0 -
. l
Base Timer
Bit 15
Overflow Signal
BT1R bit
in IIO4IR register
Base Timer
Bit 14 Overflow
Signal
BT1R bit
in IIO4IR register
Base Timer
u
0
1
p
, 7
0
1
(
2
M
The above applies to the following conditions:
• The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
• The UD1 and UD0 bits in the G1BCR1 register are set to "01
The above applies to the following conditions:
• The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register)
• The UD1 and UD0 bits in the G1BCR1 register are set to "01
The above applies to the following conditions:
• Value of G1PO0 register: "8000
• The UD1 and UD0 bits in the G1BCR1 register are set to "01
0
0
3
5
2
C
8 /
Page 285
4000
8000
C000
, 4
FFFF
0000
8000
FFFF
8002
8000
0000
M
16
16
16
16
16
16
"1"
"1"
"0"
"0"
3
16
16
16
16
"1"
"0"
"1"
"0"
2
C
f o
8 /
4
4
) T
9
5
16
"
2
2
2
" (counter increment/decrement mode)
" (counter increment/decrement mode)
" (counter increment/decrement mode)
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
22. Intelligent I/O (Base Timer)
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