HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 185
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Table 6.2
6.4.3
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (section 6.6, Basic Bus Interface and section 6.7,
Burst ROM Interface) should be referred to for further details. Note that the ROM is always
enabled and no external extended mode in the H8S/2212 Group.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled extended mode, all of area 0 is
external space. In ROM-enabled extended mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 to 6: In external extended mode, all of areas 1 to 6 is external space. When area 1 to 5
external space is accessed, the CS1 to CS5 pin signals respectively can be output. Only the basic
bus interface can be used for areas 1 to 5. Area 6 is only for the on-chip USB. For details, see
section 14, Universal Serial Bus (USB).
Area 7: Area 7 includes the on-chip RAM and internal l/O registers. In external extended mode,
the space excluding the reserved area (for details, see section 3.4, Memory Map in Each Operating
Mode) the on-chip RAM and internal l/O registers except on-chip RTC, is external space. The on-
chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when
ABWCR
ABWn
0
1
Bus Interface for Each Area
ASTCR
ASTn
0
1
0
1
Bus Specifications for Each Area (Basic Bus Interface)
WCRH, WCRL
Wn1
⎯
0
1
⎯
0
1
Wn0
⎯
0
1
0
1
⎯
0
1
0
1
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
Number of
Access States
2
3
2
3
Rev.7.00 Dec. 24, 2008 Page 129 of 698
Number of
Program Wait States
0
0
1
2
3
0
0
1
2
3
REJ09B0074-0700
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