HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 191
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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6.6.2
Table 6.3 shows the data buses used and valid strobes for the access spaces in the H8S/2218
Group.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
The RD, HWR, and LWR signals are not available in the H8S/2212 Group.
Table 6.3
Notes:
Hi-Z:
Invalid: Input state: input value is ignored.
Area
8-bit access
space
16-bit
access
space
High impedance.
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
Valid Strobes
Data Buses Used and Valid Strobes
Access
Size
Byte
Byte
Word
Byte size
Byte size
Word size
Longword
size
Read/
Write
Read
Write
Read
Write
Read
Write
· Even address
· Odd address
1st bus cycle
2nd bus cycle
Address
–
–
Even
Odd
Even
Odd
–
–
Valid Strobe
RD
HWR
RD
HWR
LWR
RD
HWR, LWR
D15
Upper data bus
Rev.7.00 Dec. 24, 2008 Page 135 of 698
Upper Data Bus
(D15 to D8)
Valid
Valid
Invalid
Valid
Hi-Z
Valid
D8 D7
Lower data bus
REJ09B0074-0700
D0
Lower Data Bus
(D7 to D0)
Invalid
Valid
Valid
Valid
Hi-Z
Invalid
Hi-Z
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