HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 569
HD64F2218TF24
Manufacturer Part Number
HD64F2218TF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218TF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 569 of 758
- Download datasheet (5Mb)
Section 14 Universal Serial Bus (USB)
14.5.6
Bulk-In Transfer (Dual FIFOs) (Endpoint 1)
EP1 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being
aware of this dual-FIFO configuration. However, one data write should be performed for one
FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP1PKTE at one
time after consecutively writing 128 bytes of data. EP1PKTE must be performed for each 64- byte
write.
When transmitting data to the host by bulk-in transfer, first enable the EP1 FIFO empty interrupt
by writing 1 to EP1EMPTYE in UIER1. At first, both EP1 FIFOs are empty, and so an EP1 FIFO
empty interrupt is generated immediately. The data to be transmitted is written to the data register
using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and
so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full,
EP1EMPTY is cleared to 0. If at least one FIFO is empty, UIFR1/EP1EMPTY is set to 1. When
ACK is returned from the host after data transmission is completed, the FIFO used in the data
transmission becomes empty. If the other FIFO contains valid transmit data at this time,
transmission can be continued.
When transmission of all data has been completed, write 0 to UIER1/EP1EMPTYE and disable
EXIRQ0 or EXIRQ1 interrupt requests.
Rev.7.00 Dec. 24, 2008 Page 513 of 698
REJ09B0074-0700
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