HD64F3644WV Renesas Electronics America, HD64F3644WV Datasheet - Page 265
HD64F3644WV
Manufacturer Part Number
HD64F3644WV
Description
IC H8/3644 MCU FLASH 80TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644WV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3644WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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There are two 16-bit read/write output compare registers, OCRA and OCRB, the contents of
which are always compared with FRC. When the values match, OCFA or OCFB is set to 1 in
TCSRX. If OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested.
When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value
selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin. After a reset, the
output from the FTOA or FTOB pin is 0 until the first compare match occurs.
OCRA and OCRB can be written and read by the CPU. Since they are 16-bit registers, data is
transferred between them and the CPU via a temporary register (TEMP). For details see section
9.5.3, CPU Interface.
OCRA and OCRB are initialized to H'FFFF upon reset and in standby mode, watch mode,
subsleep mode, and subactive mode.
Input Capture Registers A to D (ICRA to ICRD)
Input Capture Registers AH to DH (ICRAH to ICRDH)
Input Capture Registers AL to DL (ICRAL to ICRDL)
There are four 16-bit read only input capture registers, ICRA to ICRD.
When the falling edge of an input capture signal is input, the FRC value is transferred to the
corresponding input capture register, and the corresponding input capture flag (ICFA to ICFD) is
set to 1 in TCSRX. If the corresponding input capture interrupt enable bit (ICIAE to ICIDE) is 1 in
TCRX, a CPU interrupt is requested. The valid edge of the input signal can be selected by bits
IEDGA to IEDGD in TCRX.
ICRC and ICRD can also be used as buffer registers for ICRA and ICRB. Buffering is enabled by
bits BUFEA and BUFEB in TCRX.
Figure 9.17 shows the interconnections when ICRC operates as a buffer register of ICRA (when
BUFEA = 1). When ICRC is used as the ICRA buffer, both the rising and falling edges of the
Bit
Initial value
Read/Write
15
R
0
ICRAH, ICRBH, ICRCH, ICRDH
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
ICRA, ICRB, ICRC, ICRD
R
9
0
R
8
0
Rev. 6.00 Sep 12, 2006 page 243 of 526
R
7
0
ICRAL, ICRBL, ICRCL, ICRDL
R
6
0
R
5
0
R
4
0
R
REJ09B0326-0600
3
0
Section 9 Timers
R
2
0
R
1
0
R
0
0
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