HD64F3644WV Renesas Electronics America, HD64F3644WV Datasheet - Page 266
HD64F3644WV
Manufacturer Part Number
HD64F3644WV
Description
IC H8/3644 MCU FLASH 80TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644WV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3644WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Timers
external input signal can be selected simultaneously, by setting IEDGA ≠ IEDGC. If IEDGA =
IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9.16.
Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of
Table 9.16 Input Edge Selection during Buffer Operation
IEDGA
0
1
ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is
transferred from them to the CPU via a temporary register (TEMP). For details see section 9.5.3,
CPU Interface.
To assure input capture, the pulse width of the input capture input signal must be at least 1.5
system clocks ( ) when a single edge is selected, or at least 2.5 system clocks ( ) when both edges
are selected.
ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep
mode, and subactive mode.
Rev. 6.00 Sep 12, 2006 page 244 of 526
REJ09B0326-0600
FTIA
the input capture flag (ICF).
IEOGA BUFEA IEDGC
IEDGC
0
1
0
1
Edge detector
capture signal
and internal
generator
ICRC
Input Edge Selection
Falling edge of input capture A input signal is captured
Rising and falling edge of input capture A input signal are both captured
Rising edge of input capture A input signal is captured
Figure 9.17 Buffer Operation (Example)
ICRA
FRC
(initial value)
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