HD64F3644WV Renesas Electronics America, HD64F3644WV Datasheet - Page 66
HD64F3644WV
Manufacturer Part Number
HD64F3644WV
Description
IC H8/3644 MCU FLASH 80TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644WV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3644WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 2 CPU
2.6
CPU operation is synchronized by a system clock ( ) or a subclock (
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of or
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Rev. 6.00 Sep 12, 2006 page 44 of 526
REJ09B0326-0600
Basic Operational Timing
Access to On-Chip Memory (RAM, ROM)
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Legend:
op:
or
15
SUB
Operation field
Figure 2.10 Block Data Transfer Instruction Code
Figure 2.11 On-Chip Memory Access Cycle
T
1
8
state
op
op
7
Bus cycle
Address
Write data
Read data
T
2
state
SUB
). For details on these
0
SUB
to
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