R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 106
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Note:
2.7.6
The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch
address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to
be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is −126 to +128 bytes (–63 to +64 words) or
−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting
value should be an even number.
Page 76 of 1372
Absolute Address
Data address
Program instruction
address
*
Immediate—#xx:8/#xx:16/#xx:32
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
Not available in this LSI.
8 bits (@aa:8)
16 bits (@aa:16)
32 bits (@aa:32)
24 bits (@aa:24)
Normal Mode*
H'FF00 to H'FFFF
H'0000 to H'FFFF
H8S/2426, H8S/2426R, H8S/2424 Group
Advanced Mode
H'FFFF00 to H'FFFFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
H'000000 to H'FFFFFF
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
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