R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 133
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2426, H8S/2426R, H8S/2424 Group
4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Legend:
1:
0:
⎯: Retains value prior to execution
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Interrupt Control Mode
0
2
(EXR) are saved in the stack.
from the vector table to the PC, and program execution starts from that address.
Set to 1
Cleared to 0
Trap Instruction Exception Handling
Status of CCR and EXR after Trap Instruction Exception Handling
I
1
1
CCR
UI
⎯
⎯
I2 to I0
⎯
⎯
Section 4 Exception Handling
EXR
T
⎯
0
Page 103 of 1372
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