R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 157
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
5.4
5.4.1
The H8S/2426 Group and H8S/2426R Group each have seventeen external interrupts: NMI and
IRQ15 to IRQ0. The H8S/2424 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These
interrupts can be used to restore the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQn Interrupts (n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for
H8S/2424 Group): An IRQn interrupt is requested by an input signal at the IRQn pin. The IRQn
interrupts have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of IRQn interrupt requests can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by
When IRQn interrupt requests occur at low level of the IRQn pin, the corresponding IRQ pin
should be held low until an interrupt handling starts. Then the corresponding IRQ pin should be
set to high in the interrupt handling routine and clear the IRQnF bit in ISR to 0. Interrupts may not
be executed when the corresponding IRQ pin is set to high before the interrupt handling starts.
Detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or
output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
edge, rising edge, or both edges, at the IRQn pin.
software.
Interrupt Sources
External Interrupts
Section 5 Interrupt Controller
Page 127 of 1372
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