R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 20
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
R4F24268NVRFQV
Manufacturer:
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Quantity:
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11.5 Interrupt Sources................................................................................................................ 779
11.6 DTC Activation.................................................................................................................. 783
11.7 DMAC Activation.............................................................................................................. 783
11.8 A/D Converter Activation.................................................................................................. 783
11.9 Operation Timing............................................................................................................... 784
11.10 Usage Notes ....................................................................................................................... 793
Section 12 Programmable Pulse Generator (PPG) ............................................ 803
12.1 Features.............................................................................................................................. 803
12.2 Input/Output Pins............................................................................................................... 805
12.3 Register Descriptions ......................................................................................................... 806
12.4 Operation ........................................................................................................................... 815
Page xx of xxx
11.4.5 PWM Modes......................................................................................................... 765
11.4.6 Phase Counting Mode........................................................................................... 771
11.9.1 Input/Output Timing ............................................................................................. 784
11.9.2 Interrupt Signal Timing ........................................................................................ 789
11.10.1 Module Stop Function Setting .............................................................................. 793
11.10.2 Input Clock Restrictions ....................................................................................... 793
11.10.3 Caution on Cycle Setting ...................................................................................... 794
11.10.4 Contention between TCNT Write and Clear Operations ...................................... 794
11.10.5 Contention between TCNT Write and Increment Operations............................... 795
11.10.6 Contention between TGR Write and Compare Match .......................................... 796
11.10.7 Contention between Buffer Register Write and Compare Match ......................... 797
11.10.8 Contention between TGR Read and Input Capture............................................... 798
11.10.9 Contention between TGR Write and Input Capture.............................................. 799
11.10.10
11.10.11
11.10.12
11.10.13
11.10.14
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 807
12.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 808
12.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 809
12.3.4 PPG Output Control Register (PCR) .................................................................... 812
12.3.5 PPG Output Mode Register (PMR) ...................................................................... 813
12.4.1 Output Timing ...................................................................................................... 816
12.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 817
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 818
12.4.4 Non-Overlapping Pulse Output............................................................................. 819
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 821
Contention between Buffer Register Write and Input Capture ..................... 800
Contention between Overflow/Underflow and Counter Clearing................. 801
Contention between TCNT Write and Overflow/Underflow........................ 802
Multiplexing of I/O Pins ............................................................................... 802
Interrupts and Module Stop Mode ................................................................ 802
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