R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 383
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2426, H8S/2426R, H8S/2424 Group
7.5.3
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Table 7.6
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Register
23
23
H'FF
15
Idle Mode
15
Register Functions in Idle Mode
ETCR
MAR
IOAR
0
0
0
Source
address
register
Destination
address
register
Transfer counter
DTDIR = 0 DTDIR = 1 Initial Setting
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Section 7 DMA Controller (DMAC)
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
Page 353 of 1372
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