R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 405
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2426, H8S/2426R, H8S/2424 Group
(2)
Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Address bus
Full Address Mode (Cycle Steal Mode)
TEND
HWR
LWR
RD
φ
Bus release
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)
DMA
read
DMA
write
Bus release
DMA
read
DMA
write
Bus release
DMA
read
Section 7 DMA Controller (DMAC)
Last transfer
cycle
DMA
write
DMA
dead
Page 375 of 1372
Bus
release
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