R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 459
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
(2)
In burst mode, once the EXDMAC acquires the bus it continues transferring data, without
releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external
request mode.
In burst mode, once transfer is started it is not interrupted even if there is a transfer request from
another channel with higher priority. When the burst mode channel finishes its transfer, it releases
the bus in the next cycle in the same way as in cycle steal mode.
When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is
executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared
to 0.
If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is
terminated.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during burst transfer. If there is no bus request, burst transfer is executed even if the
BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Burst Mode
Bus cycle
Bus cycle
Transfer conditions:
Transfer conditions:
Auto request mode, BGUP = 0
Auto request mode, BGUP = 1
CPU
CPU
Figure 8.6 Examples of Timing in Burst Mode
EXDMAC
CPU
EXDMAC
EXDMAC operates alternately with CPU
CPU
EXDMAC
EXDMAC
CPU cycle not generated
EXDMAC
CPU
Section 8 EXDMA Controller (EXDMAC)
EXDMAC
CPU
CPU
CPU
Page 429 of 1372
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