D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 1094

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev.4.00 Sep. 07, 2007 Page 1062 of 1210
REJ09B0245-0400
Short address mode
Bit
DMABCRH
Initial value
Read/Write
:
:
:
:
Channel 1 Full Address Enable
FAE1
R/W
0
1
15
0
Short address mode
Full address mode
Channel 0 Full Address Enable
0
1
FAE0
R/W
14
0
Short address mode
Full address mode
Channel 1B Single Address Enable
SAE1
R/W
13
0
1
0
Transfer in dual address mode
Transfer in single address mode
SAE0
Channel 0B Single Address Enable
R/W
12
0
0
1
Transfer in dual address mode
Transfer in single address mode
Channel 1B Data Transfer Acknowledge
DTA1B
R/W
1
0
11
0
Clearing of selected internal interrupt
source at time of DMA transfer is disabled
Clearing of selected internal interrupt
source at time of DMA transfer is enabled
Channel 1A Data Transfer Acknowledge
1
DTA1A
0
R/W
10
0
Clearing of selected internal interrupt source
at time of DMA transfer is disabled
Clearing of selected internal interrupt
source at time of DMA transfer is enabled
Channel 0B Data Transfer Acknowledge
1
0
DTA0B
R/W
9
0
Clearing of selected internal interrupt source
at time of DMA transfer is disabled
Clearing of selected internal interrupt
source at time of DMA transfer is enabled
Channel 0A Data Transfer Acknowledge
DTA0A
1
0
R/W
8
0
Clearing of selected internal interrupt
source at time of DMA transfer is
disabled
Clearing of selected internal
interrupt source at time of DMA
transfer is enabled
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