D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 1166
D12332VFC20V
Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12332VFC20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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TSTR—Timer Start Register
TSYR—Timer Synchro Register
Rev.4.00 Sep. 07, 2007 Page 1134 of 1210
REJ09B0245-0400
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note:
If 0 is written to the CST bit during operation with the TIOC pin designated for output,
the counter stops but the TIOC pin output compare output level is retained. If TIOR is
written to when the CST bit is cleared to 0, the pin output level will be changed to the
set initial output value.
:
:
:
:
:
:
Notes:
—
—
—
—
7
0
7
0
1.
2.
To set synchronous operation, the SYNC bits for at least two channels must
be set to 1.
To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to CCLR0 in TCR.
—
—
—
—
6
0
6
0
SYNC5
Timer Synchronization
CST5
R/W
R/W
0
1
5
0
5
0
TCNTn operates independently (TCNT presetting/
clearing is unrelated to other channels)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
SYNC4
CST4
R/W
R/W
4
0
4
0
SYNC3
H'FFC0
H'FFC1
R/W
Counter Start
CST3
R/W
3
0
0
1
3
0
TCNTn count operation is stopped
TCNTn performs count operation
SYNC2
R/W
CST2
R/W
2
0
2
0
SYNC1
R/W
CST1
1
0
R/W
1
0
(n = 5 to 0)
SYNC0
R/W
CST0
0
0
R/W
(n = 5 to 0)
0
0
TPU
TPU
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