D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 172
D12332VFC20V
Manufacturer Part Number
D12332VFC20V
Description
IC H8S/2332 MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12332VFC20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.2.4
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for areas 2 to 5 and area 0.
BCRH is initialized to H'D0 by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
0
1
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface
area.
Bit 5
BRSTRM
0
1
Rev.4.00 Sep. 07, 2007 Page 140 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bus Control Register H (BCRH)
:
:
Description
Idle cycle not inserted in case of successive external read cycles in different areas.
Idle cycle inserted in case of successive external read cycles in different areas.
Description
Idle cycle not inserted in case of successive external read and external write cycles.
Idle cycle inserted in case of successive external read and external write cycles.
Description
Area 0 is basic bus interface area
Area 0 is burst ROM interface area
ICIS1
R/W
7
1
ICIS0
R/W
6
1
BRSTRM BRSTS1 BRSTS0 RMTS2
R/W
5
0
R/W
4
1
R/W
0
3
R/W
2
0
RMTS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
RMTS0
R/W
0
0
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