D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 184

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.3.4
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (section 6.4, Basic Bus Interface, section 6.5,
DRAM Interface, and section 6.7, Burst ROM Interface) should be referred to for further details.
Area 0: Area 0 includes on-chip ROM, and in expanded mode with on-chip ROM disabled, all of
area 0 is external space. In expanded mode with on-chip ROM enabled, the space excluding on-
chip ROM is external space.
When area 0 external space is accessed, the CS
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 and 6: In external expanded mode, all of area 1 and area 6 is external space.
When area 1 and 6 external space is accessed, the CS
respectively.
Only the basic bus interface can be used for areas 1 and 6.
Areas 2 to 5: In external expanded mode, areas 2 to 5 are all external space.
When area 2 to 5 external space is accessed, signals CS
Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface,
signals CS
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
When area 7 external space is accessed, the CS
Only the basic bus interface can be used for the area 7 memory interface.
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REJ09B0245-0400
Advanced Mode
2
to CS
5
are used as RAS signals.
0
7
signal can be output.
signal can be output.
1
and CS
2
to CS
6
5
pin signals can be output,
can be output.