D12332VFC20V Renesas Electronics America, D12332VFC20V Datasheet - Page 253

• Manufacturer Part Number: D12332VFC20V
• Description: IC H8S/2332 MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3
Full address mode transfer is performed with channels A and B together. For details of full address
mode setting, see table 7.4.
7.3.1
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination memory address can be updated automatically. For details, see section 7.3.4,
DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.3.2
IOAR is not used in full address transfer.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Register Descriptions (2) (Full Address Mode)
Memory Address Register (MAR)
I/O Address Register (IOAR)
:
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
31
15
—
—
0
*
30
14
—
—
0
*
29
13
—
—
0
*
28
12
—
—
0
*
27
11
—
—
0
*
26
10
—
—
0
*
25
—
—
0
9
*
24
—
— R/W R/W R/W R/W R/W R/W R/W R/W
0
8
*
Rev.4.00 Sep. 07, 2007 Page 221 of 1210
23
7
*
*
22
6
*
*
21
*
5
*
20
4
*
*
19
REJ09B0245-0400
3
*
*
18
*
2
*
*: Undefined
17
1
*
*
16
*
0
*