D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 15
D12332VFC25
Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of D12332VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25
HD6412332VFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.2
4.3
4.4
4.5
4.6
4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
4.1.2
4.1.3
Reset ................................................................................................................................. 90
4.2.1
4.2.2
4.2.3
4.2.4
Traces................................................................................................................................ 92
Interrupts ........................................................................................................................... 93
Trap Instruction................................................................................................................. 94
Stack Status after Exception Handling.............................................................................. 94
Notes on Use of the Stack ................................................................................................. 95
Overview........................................................................................................................... 97
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 100
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 105
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 113
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ...................................................................................................................... 123
5.5.1
5.5.2
5.5.3
5.5.4
Exception Handling Operation............................................................................. 88
Exception Vector Table ....................................................................................... 88
Overview.............................................................................................................. 90
Reset Sequence .................................................................................................... 90
Interrupts after Reset............................................................................................ 91
State of On-Chip Supporting Modules after Reset Release ................................. 91
Features................................................................................................................ 97
Block Diagram..................................................................................................... 98
Pin Configuration................................................................................................. 99
Register Configuration......................................................................................... 99
System Control Register (SYSCR) ...................................................................... 100
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 101
IRQ Enable Register (IER) .................................................................................. 102
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 103
IRQ Status Register (ISR).................................................................................... 104
External Interrupts ............................................................................................... 105
Internal Interrupts................................................................................................. 107
Interrupt Exception Vector Table ........................................................................ 107
Interrupt Control Modes and Interrupt Operation ................................................ 113
Interrupt Control Mode 0 ..................................................................................... 116
Interrupt Control Mode 2 ..................................................................................... 118
Interrupt Exception Handling Sequence .............................................................. 120
Interrupt Response Times .................................................................................... 122
Contention between Interrupt Generation and Disabling..................................... 123
Instructions That Disable Interrupts..................................................................... 124
Times when Interrupts Are Disabled ................................................................... 124
Interrupts during Execution of EEPMOV Instruction.......................................... 124
.......................................................................................... 97
Rev.4.00 Sep. 07, 2007 Page xiii of xxx
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