D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 167
D12332VFC25
Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of D12332VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25
HD6412332VFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.2.2
ASTCR is an 8-bit readable/writable register that designates each area as either 2-state access
space or 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
ASTCR is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as 2-state access space or 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit n
ASTn
0
1
(n = 7 to 0)
6.2.3
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
Program waits are not inserted in on-chip memory or internal I/O register access.
WCRH and WCRL are initialized to H'FF by a reset, and in hardware standby mode. They are not
initialized in software standby mode.
Bit
Initial value :
R/W
Access State Control Register (ASTCR)
Wait Control Registers H and L (WCRH, WCRL)
:
:
Description
Area n is designated for 2-state access
Wait state insertion in area n external space access is disabled
Area n is designated for 3-state access
Wait state insertion in area n external space access is enabled
AST7
R/W
7
1
AST6
R/W
6
1
AST5
R/W
5
1
AST4
R/W
1
4
Rev.4.00 Sep. 07, 2007 Page 135 of 1210
AST3
R/W
3
1
AST2
R/W
2
1
REJ09B0245-0400
AST1
R/W
1
1
(Initial value)
AST0
R/W
0
1
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