D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 201

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

6.5.4
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
space both the upper and lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface. For details, see section
6.4.2, Data Size and Data Alignment.
6.5.5
Table 6.6 shows the pins used for DRAM interfacing and their functions.
Table 6.6
Pin
HWR
LCAS
CS
CS
CS
CS
CAS
WAIT
A
D
12
15
2
3
4
5
to A
to D
0
0
Data Bus
Pins Used for DRAM Interface
DRAM Interface Pins
With DRAM
Setting
WE
LCAS
RAS2
RAS3
RAS4
RAS5
UCAS
WAIT
A
D
12
15
to A
to D
0
0
Name
Write enable
Lower column
address strobe
Row address
strobe 2
Row address
strobe 3
Row address
strobe 4
Row address
strobe 5
Upper column
address strobe
Wait
Address pins
Data pins
I/O
Output
Output
Output
Output
Output
Output
Output
Input
Output
I/O
15
Rev.4.00 Sep. 07, 2007 Page 169 of 1210
15
to D
Function
Write enable for DRAM space access
when 2-CAS access is set
Lower column address strobe signal for
16-bit DRAM space access
Row address strobe when area 2 is
designated as DRAM space
Row address strobe when area 3 is
designated as DRAM space
Row address strobe when area 4 is
designated as DRAM space
Row address strobe when area 5 is
designated as DRAM space
Upper column address strobe for DRAM
space access
Wait request signal
Row address/column address
multiplexed output
Data input/output pins
to D
8
, is enabled, while in 16-bit DRAM
0
, are enabled.
REJ09B0245-0400