D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 241

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

7.2.2
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source
address or destination address. The upper 8 bits of the transfer address are automatically set to
H'FF.
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is invalid in single address mode.
IOAR is not incremented or decremented each time a transfer is executed, so the address specified
by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
7.2.3
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of
this register is different for sequential mode and idle mode on the one hand, and for repeat mode
on the other.
Sequential Mode and Idle Mode
Bit
IOAR
Initial value :
R/W
Transfer Counter (ETCR)
Bit
Initial value :
R/W
I/O Address Register (IOAR)
Execute Transfer Count Register (ETCR)
:
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15
15
*
*
14
14
*
*
13
13
*
*
12
12
*
*
11
11
*
*
10
10
*
*
9
9
*
*
8
*
8
*
Rev.4.00 Sep. 07, 2007 Page 209 of 1210
7
7
*
*
6
6
*
*
5
*
5
*
4
4
*
*
REJ09B0245-0400
3
3
*
*
2
*
2
*
*: Undefined
*: Undefined
1
1
*
*
0
*
0
*