D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 678

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Section 14 Serial Communication Interface (SCI)
Clock
Either an internal clock generated by the built-in baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1
and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive
operations in units of one character, an external clock should be selected as the clock source.
Data Transfer Operations
SCI initialization (synchronous mode): Before transmitting or receiving data, first clear the TE
and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 14.15 shows a sample SCI initialization flowchart.
Rev.4.00 Sep. 07, 2007 Page 646 of 1210
REJ09B0245-0400