D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 183
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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6.5.9
When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column
address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external
data bus are output. In the case of × 16-bit organization DRAM, the 2-CAS type can be connected.
Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the
selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and
corresponding output pin selections.
When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only
UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0,
PB5 can be used as an input/output port.
Note that RAS down mode cannot be used when a device other than DRAM is connected to
external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is
always inserted when an external access to other than DRAM space occurs after a DRAM space
access. For details, see section 6.9, Idle Cycle.
Table 6.8
CSEL
0
1
Figure 6.19 shows the control timing.
Byte Access Control and CAS Output Pin
CSEL Settings and UCAS and LCAS Output Pins
UCAS
PB4
HWR
LCAS
PB5
LWR
Rev.5.00 Sep. 12, 2007 Page 153 of 764
REJ09B0396-0500
6. Bus Controller
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