D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 435
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Table 11.3 TPC Operating Conditions
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 11.3.4, Non-Overlapping TPC Output.
11.3.2
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
NDER
0
1
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Output Timing
φ
16TCNT
GRA
Compare
match A signal
NDRB
PBDR
TP to TP
8
DDR
0
1
0
1
15
Generic input port
Generic output port
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
TPC pulse output
Pin Function
m
m
N
11. Programmable Timing Pattern Controller (TPC)
Rev.5.00 Sep. 12, 2007 Page 405 of 764
N
n
N + 1
n
n
REJ09B0396-0500
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