D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 446
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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12. Watchdog Timer
12.2.2
TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and
clock source.
Bit
Initial value
Read/Write
Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Bit 7⎯Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Rev.5.00 Sep. 12, 2007 Page 416 of 764
REJ09B0396-0500
Bit 7
OVF
0
1
Access.
* Only 0 can be written, to clear the flag.
Timer Control/Status Register (TCSR)
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
[Setting condition]
Set when TCNT changes from H'FF to H'00
R/(W)
Overflow flag
Status flag indicating overflow
OVF
7
0
*
WT/IT
Timer mode select
Selects the mode
R/W
6
0
Timer enable
TME
Selects whether TCNT runs or halts
R/W
5
0
⎯
⎯
4
1
Reserved bits
⎯
⎯
3
1
CKS2
R/W
2
0
Clock select
These bits select the
TCNT clock source
CKS1
R/W
1
0
(Initial value)
CKS0
R/W
0
0
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