C8051F020-GQR Silicon Laboratories Inc, C8051F020-GQR Datasheet - Page 128
C8051F020-GQR
Manufacturer Part Number
C8051F020-GQR
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F020-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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C8051F020/1/2/3
13.1. Power-on Reset
The C8051F020/1/2/3 family incorporates a power supply monitor that holds the MCU in the reset state until VDD
rises above the V
trical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the 100 ms
VDD Monitor timeout in order to allow the VDD supply to stabilize.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset flags
in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all resets cause program exe-
cution to begin at the same location (0x0000), software can read the PORSF flag to determine if a power-up was the
cause of reset. The contents of internal data memory should be assumed to be undefined after a power-on reset.
The VDD monitor function is enabled by tying the MONEN pin directly to VDD. This is the recommended
configuration for the MONEN pin.
.
13.2. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below V
drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level above VRST, the CIP-51
will leave the reset state in the same manner as that for the power-on reset (see Figure 13.2). Note that even though
internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped
below the level required for data retention. If the PORSF flag is set to logic 1, the data may no longer be valid.
128
Logic HIGH
Logic LOW
2.70
2.55
RST
2.0
1.0
level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for the Elec-
/RST
V
RST
Figure 13.2. Reset Timing
Power-On Reset
100ms
Rev. 1.4
VDD Monitor Reset
RST
, the power supply monitor will
100ms
t
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