MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 108

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EEDIVH — EEPROM Modulus Divider
EEDIVL — EEPROM Modulus Divider
EEPROM Memory
8.5 EEPROM Control Registers
Technical Data
108
1. Loaded from SHADOW word.
1. Loaded from SHADOW word.
RESET:
RESET:
CAUTION:
EEDIV7
Bit 7
Bit 7
—
0
0
(1)
EEDIV6
—
6
0
0
6
(1)
A steady internal self-time clock is required to provide accurate counts
to meet EEPROM program/erase requirements. This clock is generated
via a programmable 10-bit prescaler register. Automatic program/erase
termination is also provided.
In ordinary situations, with crystal operating properly, the steady internal
self-time clock is derived from the input clock source (EXTALi). The
divider value is as in EEDIVH:EEDIVL. In limp-home mode, where the
oscillator clock has malfunctioned or is unavailable, the self-time clock is
derived from the PLL at a nominal f
value of $0023. Program/erase operation is not guaranteed in limp-
home mode.
It is strongly recommended that program/erase operation is terminated
in the event of loss of crystal, either by the application software (clearing
EEPGM & EELAT bits) when entering limp home mode or by enabling
the clock monitor to generate a clock monitor reset. This will prevent
unnecessary stress on the emulated EEPROM during oscillator failure.
EEDIV5
—
5
0
0
5
(1)
EEDIV4
EEPROM Memory
—
4
0
0
4
(1)
EEDIV3
—
3
0
0
3
(1)
VCOMIN
EEDIV2
—
2
0
0
2
(1)
using a predefined divider
EEDIV9
EEDIV1
MC68HC912D60A — Rev. 3.1
—
—
1
1
(1)
(1)
Freescale Semiconductor
EEDIV8
EEDIV0
Bit 0
—
Bit 0
—
(1)
(1)
$00EE
$00EF