MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 115

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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8.6 Program/Erase Operation
8.7 Shadow Word Mapping
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
A program or erase operation should follow the sequence below if AUTO
bit is clear:
If the AUTO bit is set, steps 4 and 5 can be replaced by a step to poll the
EEPGM bit until it is cleared.
It is possible to program/erase more bytes or words without intermediate
EEPROM reads, by jumping from step 5 to step 2.
The shadow word is mapped to location $_FC0 and $_FC1 when the
NOSHW bit in EEMCR register is zero. The value in the shadow word is
loaded to the EEMCR, EEDIVH and EEDIVL after reset.
shows the mapping of each bit from shadow word to the registers
1. Reserved for testing. Must be set to one in user application.
2. Reserved. Must be set to one in user application for future compatibility.
1. Write BYTE, ROW and ERASE to desired value, write EELAT = 1
2. Write a byte or an aligned word to an EEPROM address
3. Write EEPGM = 1
4. Wait for programming,
5. Write EEPGM = 0
6. Write EELAT = 0
Shadow word location
$_FC0, bit 3:2
$_FC0, bit 1:0
$_FC1, bit 7:0
$_FC0, bit 6
$_FC0, bit 5
$_FC0, bit 4
$_FC0 bit 7
EEPROM Memory
Table 8-4. Shadow word mapping
t
PROG
or erase,
t
ERASE
EEMCR / NOBDML
EEMCR / FPOPEN
EEDIVCLK / bit 7:0
EEMCR / NOSHW
EEMCR / bit 5
EEDIVH / bit 1:0
not mapped
Register / Bit
delay time (10ms)
Program/Erase Operation
EEPROM Memory
Table 8-4
(2)
(1)
Technical Data
115

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