MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 123

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5 Interrupt Control and Priority Registers
INTCR — Interrupt Control Register
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
IRQE
Bit 7
0
IRQEN
6
1
IRQE — IRQ Select Edge Sensitive Only
IRQEN — External IRQ Enable
DLY — Enable Oscillator Start-up Delay on Exit from STOP
IRQE can be read anytime and written once in normal modes. In
special modes, IRQE can be read anytime and written anytime,
except the first write is ignored.
The IRQ pin has an active pull-up. See
IRQEN can be read and written anytime in all modes.
The delay time of about 4096 cycles is based on the X clock rate
chosen.
DLY can be read anytime and written once in normal modes. In
special modes, DLY can be read and written anytime.
0 = IRQ configured for low-level recognition.
1 = IRQ configured to respond only to falling edges (on pin
0 = External IRQ pin is disconnected from interrupt logic.
1 = External IRQ pin is connected to interrupt logic.
0 = No stabilization delay imposed on exit from STOP mode. A
1 = Stabilization delay is imposed before processing resumes after
DLY
5
1
PE1/IRQ).
stable external oscillator must be supplied.
STOP.
Resets and Interrupts
4
0
0
3
0
0
2
0
0
Interrupt Control and Priority Registers
Table
1
0
0
3-4.
Resets and Interrupts
Bit 0
0
0
Technical Data
$001E
123