MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 128

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
203
Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Resets and Interrupts
9.9 Customer Information
Technical Data
128
required to complete the instruction. Some of the longer instructions can
be interrupted and will resume normally after servicing the interrupt.
When the CPU begins to service an interrupt, the instruction queue is
cleared, the return address is calculated, and then it and the contents of
the CPU registers are stacked as shown in
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt
service request is pending) is set to prevent other interrupts from
disrupting the interrupt service routine. The interrupt vector for the
highest priority source that was pending at the beginning of the interrupt
sequence is fetched, and execution continues at the referenced location.
At the end of the interrupt service routine, an RTI instruction restores the
content of all registers from information on the stack, and normal
program execution resumes.
If another interrupt is pending at the end of an interrupt service routine,
the register unstacking and restacking is bypassed and the vector of the
interrupt is fetched.
Before disabling an interrupt using a local interrupt control bit, set the I
mask bit in the CCR. Failing to do so may cause an SWI interrupt to be
fetched instead of the vector for the interrupt source that was disabled.
Table 9-2. Stacking Order on Entry to Interrupts
Resets and Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
CPU Registers
RTN
Y
X
Table
B : A
CCR
H
H
H
MC68HC912D60A — Rev. 3.1
: RTN
: Y
: X
L
L
9-2.
Freescale Semiconductor
L

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