MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 132

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O Ports with Key Wake-up
KWIEG — Key Wake-up Port G Interrupt Enable Register
KWIEH — Key Wake-up Port H Interrupt Enable Register
Technical Data
132
RESET:
RESET:
KWIEH7
WI2CE
Bit 7
Bit 7
0
0
KWIEG6
KWIEH6
6
0
6
0
Read and write anytime.
WI2CE — Wake-up I
KWIEG[6:0] — Key Wake-up Port G Interrupt Enables
Read and write anytime.
KWIEH[7:0] — Key Wake-up Port H Interrupt Enables
When WI2CE is set, PG6 and PG7 operate in wired-OR or open-drain
mode.
The I
SDA line when SCL is high. When WI2CE is set, a falling edge on
PG6 (SDA) is recognized only if PG7 (SCL) is high.
Depending on WI2CE bit, KWIEG6 enables either falling edge or I
Start condition interrupt.
0 = PG6 default key wake-up on falling edge
1 = I
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
KWIEG5
KWIEH5
2
5
0
C Start condition is defined as a high to low transition of the
5
0
2
C Start condition detection on PG7 and PG6
I/O Ports with Key Wake-up
KWIEG4
KWIEH4
4
0
4
0
2
C Enable
KWIEG3
KWIEH3
3
0
3
0
KWIEG2
KWIEH2
2
0
2
0
KWIEG1
KWIEH1
MC68HC912D60A — Rev. 3.1
1
0
1
0
Freescale Semiconductor
KWIEG0
KWIEH0
Bit 0
Bit 0
0
0
$002C
$002D
2
C