MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 134

IC MCU 16BIT 112-LQFP

MC912D60CCPVE

Manufacturer Part Number
MC912D60CCPVE
Description
IC MCU 16BIT 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912D60CCPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912D60CCPVE
Manufacturer:
FREESCAL
Quantity:
203
Part Number:
MC912D60CCPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
I/O Ports with Key Wake-up
KWIFH — Key Wake-up Port H Flag Register
10.4 Key Wake-Up Input Filter
Technical Data
134
RESET:
KWIFH7
Bit 7
0
KWIFH6
6
0
Read and write anytime.
Each flag is set by a falling edge on its associated input pin. To clear the
flag, write one to the corresponding bit in KWIFH.
KWIFH[7:0] — Key Wake-up Port H Flags
The KWU input signals are filtered by a digital filter which is active only
during STOP mode. The purpose of the filter is to prevent single pulses
shorter than a specified value from waking the part from STOP.
The filter is composed of an internal oscillator and a majority voting logic.
The filter oscillator starts the oscillation by detecting a triggering edge on
an input if the corresponding interrupt enable bit is set. The majority
voting logic takes three samples of an asserted input pin at each filter
oscillator period and if two samples are taken at the triggering level, the
filter recognizes a valid triggering level and sets the corresponding
interrupt flag. In this way the majority voting logic rejects the short non-
triggering state between two incoming triggering pulses. As the filter is
shared with all KWU inputs, the filter considers any pulse coming from
any input pin for which the corresponding interrupt enable bit is set.
The timing specification is given for a single pulse. The time interval
between the triggering edges of two following pulses should be greater
than the t
0 = Falling edge on the associated bit has not occurred
1 = Falling edge on the associated bit has occurred (an interrupt
KWIFH5
5
0
KWSP
will occur if the associated enable bit is set)
I/O Ports with Key Wake-up
in order to be considered as a single pulse by the filter. If
KWIFH4
4
0
KWIFH3
3
0
KWIFH2
2
0
KWIFH1
MC68HC912D60A — Rev. 3.1
1
0
Freescale Semiconductor
KWIFH0
Bit 0
0
$002F

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